The present invention relates generally to MOS (metal oxide semiconductor) memories, and is particularly directed to an improved redundancy scheme for use in such a memory.
MOS memories generally include a memory array in the form of rows and columns of main memory cells for storing digital data. In a typical memory, there are thousands of individual memory cells, each of which must function properly. A single inoperative memory cell destroys the usefulness of the memory and, therefore, lowers the yield of the wafer on which many memories are simultaneously manufactured.
To increase the yield of each wafer, it has been proposed to include spare memory cells in each chip. Thus, if a main memory cell is found to be defective during testing by the manufacturer, a spare memory cell is selected to replace the defective memory cell.
Some prior schemes for selecting spare memory cells include a single spare column of cells for replacing a main column of cells in which a defective cell is located. Although such schemes evidently perform their limited function, they are incapable of "fixing" larger defects in the memory which may render inoperative one or more columns (or rows) of main cells.
Prior redundancy schemes also suffer from other disadvantages. For example, some are implemented in a manner that causes an undesirably large amount of standby power to be dissipated. In addition, relatively complex circuitry has usually been required to implement the redundancy scheme, and the access time of the memory has been impaired. For these and other reasons, prior redundancy schemes have not been entirely satisfactory.